The present invention generally relates to signal processing circuits, and in particular to a signal processing circuit for delaying an input signal by a predetermined time. The present invention is applicable to filter circuits for an analog signal or a digital signal.
As well known, delay circuits are widely used as a signal processing circuit for delaying an input signal by a predetermined time. The delay circuits are generally classified into two types, one of which is an analog delay circuit and the other is a digital delay circuit. For example, ultrasonic delay lines such as a comb line filter are known as an analog delay circuit, and shift registers are known as a digital delay circuit. It is also well known that the delay circuits are used for filters for filtering an input signal to produce an output signal having desirable frequency components.
However, the conventional delay circuits using the ultrasonic delay lines have a disadvantage that the size is physically limited and therefore the delay circuits of the compact size are not obtainable.
On the other hand, the conventional delay circuits using the shift registers have a disadvantage that a number of shift registers to be connected in series increases as a delay amount (delay time) is increased. For this reason, the scales of the delay circuits become large as the delay amount of increases.
Moreover, when it is desired to eliminate some frequency components from the input signal, it is necessary to adjust the clock frequency or to vary the number of the shift registers forming the delay circuit 12. In other words, the frequency components to be eliminated are not changed even when the frequency of the input signal varies.